1. Field of the Invention
The invention relates generally to machine language instructions and more particularly to methods for executing machine language instructions.
2. Description of the Related Art
A typical data processor is capable of executing programs written in any of a variety of programming languages. Before execution, however, each program is converted into a sequence of machine language instructions. Each machine language instruction ordinarily includes an opcode field which specifies an operation to be performed and a nonopcode field which, for example, may specify the data which is to be operated upon. For example, the opcode field of one type of machine language instruction specifies that certain registers be loaded with data currently stored at one or more memory locations in the data processor, and the nonopcode field includes operands which specify the addresses of the memory locations of the data to be loaded.
The execution of a machine language instruction by a data processor usually involves the execution by the data processor of multiple hardware level operations known as microoperations. The sequencing and control ofo microoperations involved in the execution of a machine language instruction often is achieved through the use of a microprogram stored in a control unit of the data processor. Such a microprogram, for example, may comprise an algorithm or an instruction set comprising an ordered sequence of instructions which control the execution of the microoperations involved in the execution of a machine language instruction.
Thus, the execution of respective machine language instructions ordinarily requires the linking of hte respective instructions to respective microprograms used to execute the instructions. The efficient linking of instructions and microprograms often can be a challenging task, especially where different respective machine language instructions have similar opcodes.
For example, at least one earlier data processor utilized a set of machine language instructions comprising two byte, sixteen bit, opcodes in which the respective first bytes of the opcodes of the instructions in the set were identical. One possible procedure to distinguish between the instructions of the set was to provide a one cycle 256-way branch. However, a 256-way branch would be wasteful of hardward resources since far fewer than 256 different microprograms were needed to sequence and control the various microoperations involved in the execution of the different machine language instructions in the set. Another procedure to distinguish between the instructions was to execute a microprogram branching algorithm which required several data processor clock cycles to complete. Unfortunately, the use of such an algorithm could slow the execution of the machine language instructions in the set to an unacceptable degree because it required too many data processor clock cycles to complete.
Consequently, another alternative procedure known as mapping often was used to distinguish between instructions having similar opcodes. In at least one earlier data processor, for example, mapping was accomplished by entering the entire two byte opcode of a respective machine language instruction into an instruction data register. The respective machine language instruction in the instruction data register was provided to mapping circuitry which generated a respective address signal combination corresponding to an address location in the control unit of the data processor. That address location typically was the location of starting microinstructions of a microprogram used for sequencing and controlling the microoperations involved in the execution of the respective machine language instruction.
While earlier methods for executing machine language instructions using respective microprograms stored in a control unit of a data processor generally have been accpeptable, there have been shortcomings with the execution of machine language instructions where certain operands occur in the nonopcode fields of those instructions significantly more frequently than other operands. More particularly, there have been problems in achieving a proper balance between the number of data processor clock cycles used to execute such instructions and the amount of hardware resources which must be dedicated to the execution of the instructions.
For example, in one particular data processor, one type of instruction known as a load control instruction caused the loading of any of a finite number of respective combinations of control registers of a data processor control unit with parameters used to control the operation of the data processor. Thus, the load control instruction could include any one of a finite number of different respective operands in the nonopcode field of the instruction which respectively corresponded to the different respective combinations of control registers to be loaded.
One possible procedure for executing the load control instruction involved the use of a single microprogram algorithm to load any respective combination of control registers designated in the nonopcode field of the instruction. The procedure would use the same algorithm regardless of which respective combination of control registers was designated by the nonopcode field of the instruction. In practice, however, certain combinations of control registers were loaded more frequently in the course of data processor operation than were other combinations. Therefore, it was desirable to utilize a procedure for executing the load control instruction which minimized the time necessary to load the most frequently loaded register combinations. Unfortunately, the use of the same algorithm regardless of which respective combination of control registers was to loaded did not result in such minimization.
Moreover, in order to optimize the usage of hardware resources, it frequently could be desirable to avoid unnecessary branching in the course of the execution of the load control instruction in the loading of the less frequently loaded register combinations. Thus, minimizing the time necessary to load the least frequently loaded register combinations through branching could be wasteful of hardware resources and often was not desirable.
Thus, there has existed a need for an improved method for executing machine language instructions, especially those instructions in which certain nonopcode field values occur significantly more frequently than others. The present invention meets this need.